1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of manufacturing semiconductor devices that is capable of reducing defects and pits on a surface of a semiconductor substrate during the manufacturing of the semiconductor devices.
2. Description of the Related Art
Semiconductor manufacturing processes usually include forming isolations for electrically isolating adjacent active devices, such as transistors, in a semiconductor substrate. Among such isolation technologies, a local oxidation of silicon (LOCOS) method is well known. In accordance with the LOCOS method, an isolation commonly known as a field oxide is formed by oxidizing silicon in the semiconductor substrate. The LOCOS method, however, suffers from several problems. Some of these problems will be now described.
First, a bird""s beak is formed at side edges of the isolation, thereby making it difficult to secure a desired size of the isolation. While there may be a solution to achieve the desired size of the isolation (i.e., the field oxide), the solution includes performing subsequent processes such as removing the bird""s beak after forming the field oxide with the bird""s beak, so that the manufacturing processes of the semiconductor device becomes increasingly complicated.
Second, the silicon substrate becomes enlarged at isolation areas during the oxidizing of the substrate. Therefore, a height difference exists between the isolation areas and active areas in which transistors are to be formed. Accordingly, when a polysilicon layer is formed on a semiconductor substrate having the isolations and then patterned to form gate electrodes of the transistors, the height difference causes dispersion of light for photolithography. As a result, a process margin of the photolithography is reduced so that a desired length of the gate electrode is not able to be secured.
Third, electric characteristics of the semiconductor devices formed on a semiconductor substrate having such narrowed isolations are degraded. That is, electric punch through between adjacent active areas may easily occur due to a narrow width of the isolation interposing the adjacent active areas. A narrow width of an isolation means a physically reduced field channel length and thus latch up phenomenon is caused. Latch up causes undesired circuit operations in a logic circuit area in which a plurality of logic circuits are formed and reduces charge retention time in a memory cell area, thereby increasing refresh frequency of the memory cells.
Therefore, as a design rule of a semiconductor device is reduced, the LOCOS method has been replaced with a shallow trench isolation (STI) method from the range of a 0.25 xcexcm design rule.
In the STI method, the isolations are formed by first forming shallow trenches in a semiconductor substrate, then filling the shallow trenches with an oxide material and planarizing an upper surface of the semiconductor substrate. Accordingly, the planarization process eliminates a step height difference between active areas and isolation areas. That is, the surface of the semiconductor substrate with the isolations is substantially even. Accordingly, a gate electrode can be formed with sufficient process margin. Further, it is relatively easy to secure the desired size of the isolation because a bird""s beak is not formed, thereby inhibiting the occurrence of the punch through effect.
A conventional method of manufacturing a semiconductor device will now be described.
FIGS. 1A through 1H illustrate partial cross-sectional views of a semiconductor substrate sequentially showing a conventional method of forming a semiconductor device. The conventional semiconductor device manufacturing method includes an isolation process of the STI method.
Referring to FIG. 1A, a first oxide layer 2 is formed on a semiconductor substrate 1 and then a first silicon nitride layer 3 and an anti-reflection layer 4 are formed on the first oxide layer 2.
Next, as shown in FIG. 1B, a photolithography process is performed onto the semiconductor substrate 1 to divide the semiconductor substrate into active areas and inactive areas. Then, a trench 5 is formed at an inactive area in the semiconductor substrate by an etching process.
The first oxide layer 2 is formed using a thermal oxidation process and has a thickness of 120 xc3x85. The first oxide layer 2 is formed to reduce lattice defects of the semiconductor substrate during etching the first silicon nitride 3 for forming the trench at the inactive area. The lattice defects are caused by plasma damage during the etching step. The first silicon nitride layer 3 is used as a mask to protect the active areas from being etched. The anti-reflection layer 4 is used to reduce reflectivity of light for photolithography, so that a fine pitch pattern may be achieved.
Next, as shown in FIG. 1C, after the trench 5 is formed, sidewalls of the trench 5 are oxidized. A second silicon nitride layer and a hot temperature oxide (HTO) layer (not shown) are deposited in the trench 5, and then a high density plasma (HDP) oxide layer 6 is formed on an entire surface of the semiconductor substrate 1. The oxidation of the sidewalls of the trench 5 is performed to cure any damage to and defects of the semiconductor substrate and to reduce a stress applied to the semiconductor substrate in the trench 5 by the second silicon nitride layer (not shown). The second silicon nitride layer protects the semiconductor substrate by preventing oxidants from permeating into the substrate. The oxidants are generated in the HDP oxide layer 6 filling the trench 5 during a heat treatment process. The HTO layer (not shown) is a buffer layer for protecting the second silicon nitride layer from being etched during the formation of the HDP layer.
Next, as shown in FIG. 1D, the semiconductor substrate 1 is planarized by a chemical mechanical polishing (CMP) process and the first silicon nitride layer 3 is removed using a wet etching process.
As shown in FIG. 1E, a photoresist layer 7 is formed on an entire surface of the semiconductor substrate and then an opening 8 is formed in the photoresist layer 7 to expose an upper surface of the HDP layer 6. Hereinafter, the formation of the opening 8 is referred to as a key opening step.
As shown in FIG. 1F, the HDP layer 6 is etched to a predetermined depth through the opening 8 using a dry etching, thereby forming an align key 9 used in a subsequent photolithography process. Then, the first oxide layer 2 on the semiconductor substrate at the active areas is removed using a wet etching process. The align key 9 is formed in a scribe line or other area other than a chip area where semiconductor devices are to be formed in a wafer.
As shown in FIG. 1G, a second oxide layer 10 is formed on an upper surface of the semiconductor substrate 1, and then impurity ions 11 are implanted into the semiconductor substrate. After implanting, the semiconductor substrate is subjected to a rapid thermal annealing (RTA) process.
The second oxide layer 10 is formed using a thermal oxidation process to a thickness of 120 xc3x85 to reduce ion implantation damage of the semiconductor substrate during implanting. The RTA process is performed at a temperature of 1050xc2x0 C. in an N2 gas atmosphere for 30 minutes to excite the impurity ions in the semiconductor substrate and to cure any damage in the semiconductor substrate.
As shown in FIG. 1H, the second oxide layer 10, having been damaged during the ion implantation, is removed using a wet etching process.
In the semiconductor device manufacturing method described above, contaminants, such as metal ions generated during the key opening step, are not completely removed from the semiconductor substrate 1 because the impurities and the metal ions have combined with the first oxide layer 2, which has permeated a lattice defect and normal lattice sites weakened during the trench etching step referred to connection with FIG. 1B, thereby making a by-product or a reaction in the semiconductor substrate 1.
Thereafter, the by-product is grown due to ion implantation and the RTA process. After the wet etching process of the second oxide layer 10, the by-product is removed from the semiconductor substrate 1 and then the lattices with the by-product make pits only at active area in the semiconductor substrate 1. That is, there is a disadvantage in that the conventional method make pits in the semiconductor substrate 1.
FIG. 2A is a wafer map showing a dispersion of pits formed on a wafer by a chip. The wafer map in FIG. 2A is acquired after removing the second oxide layer 10 referred to in connection with FIG. 1H.
FIGS. 2B and 2C are wafer maps showing the numbers of pits in memory cell areas and sense amplifier areas in a single wafer, respectively. The numerals in the rectangular (chips) indicate the numbers of pits in the memory cell area and the sense amplifier area. As shown in FIGS. 2B and 2C, the number of pits is the greatest at a central portion of the wafer and decreases at points farther away from the center of the wafer.
FIG. 2D is a vertical scanning electron microscope (VSEM) photograph illustrating the pits, the photograph being taken after the second oxide layer is removed. From this VSEM photograph, it may be seen that the pits are formed only on the active areas.
It is a feature of an embodiment of the present invention to provide a method of manufacturing a semiconductor device, including a key opening step that is performed after a rapid thermal annealing (RTA) process, thereby reducing the occurrence of pits on active areas of a semiconductor substrate.
In accordance with one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening and removing the insulation layer. Preferably, the insulation layer is an oxide layer formed using a thermal oxidation process. Also preferably, the insulation layer is formed to a thickness of about 120 xc3x85.
In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming a photoresist layer on a first insulation layer remaining from the formation of the isolation and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, removing the photoresist layer and the first insulation layer, forming a second insulation layer on an upper surface of the semiconductor substrate to a thickness of less than 120 xc3x85, implanting ions into the semiconductor substrate using the second insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, and removing the second insulation layer. Preferably, the second insulation layer is an oxide layer formed using a thermal oxidation method or a deposition process. Also preferably, the second insulation layer is formed to a thickness of less than about 65 xc3x85.
In accordance with yet another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming a photoresist layer on a first insulation layer remaining from the formation of the isolation and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, removing the photoresist layer and the first insulation layer, forming a second insulation layer on an upper surface of the semiconductor substrate, implanting ions into the semiconductor substrate using the second insulation layer as a buffer layer, etching an upper portion of the second insulation layer until the thickness of the second insulation layer is reduced to a predetermined thickness, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, and removing the second insulation layer. Preferably, the second insulation layer is formed to a thickness of between about 65 and 120 xc3x85. Preferably, during the etching of the second insulation layer, the predetermined thickness is less than about 65 xc3x85.